Our approach is based on a transition-mode, which calculates the delay for a pair of actual vectors. However, their approach was limited to a floating mode delay, which assumes that the primary inputs and all other nodes start at unknown values (X) and make one transition to a defined value. The technique presented in used a SAT- based search algorithm for leakage power reduction, while the work of used a SAT solver to compute combinational circuit delay. The idea of formulating circuit properties as decision problems is not a novel concept. They have typically only been applied on a small scale and using simple delay models. While extremely powerful, these techniques are also quite compute intensive. A common technique they use is converting a timed combinational network into a system of interacting non-deterministic finite automata, and then analyzing the system with a SAT solver. The asynchronous-verification community also models the inter- action of timing with logic (e.g., ). Min-max approaches are limited, as the existence of a short path from one input vector and a long path from another vector does not guarantee existence of intermediate paths.
However, these approaches use either static techniques or min-max switching windows. More recent work has explored modeling the effects of crosstalk on delay, input slope on delay, crosstalk on noise, and on the effect of multiple-inputs switching on delay. Unfortunately, this work was too CPU intensive to be practical. For example, STA with dynamic sensitization was well studied in the early 1990s. In addition, there has been much prior work in related areas. Post-silicon timing is starting to come into its own as a research topic. Though there are many potential sources (see, for example, ), there is little real data that identifies one as the most important. Furthermore, in doing so, it could help shed light on the relative importance of the different sources of miscorrelation between STA and measured silicon speeds. Such a tool could easily generate test patterns for the paths it finds. All delays will take into account pattern-dependent effects such as data-dependent gate delays and multiple-inputs switching. We will not only generate a critical path, but the input vector that stimulates it. For the purposes of this paper, we will focus on one application: determining the longest critical delay-path through a cone of logic. Its goal is to answer timing questions in the context of specific input patterns. In short, In this paper, we will propose a pattern-dependent delay model. each case, the reliance of post-silicon debug on patterns makes it difficult to take advantage of the large pre-silicon static timing effort, resulting in redundant effort and schedule impact.